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KM44C4003C, KM44C4103C
CMOS DRAM
4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode
DESCRIPTION
This is a family of 4,194,304 x 4 bit Quad CAS with Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle (2K Ref. or 4K Ref.), access time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode. This 4Mx4 Fast Page Mode Quad CAS DRAM family is fabricated using Samsungs advanced CMOS process to realize high bandwidth, low power consumption and high reliability.
FEATURES
* Part Identification - KM44C4003C/C-L (5V, 4K Ref.) - KM44C4103C/C-L (5V, 2K Ref.)
* Fast Page Mode operation * Four seperate CAS pins provide for separate I/O operation * CAS-before-RAS refresh capability * RAS-only and Hidden refresh capability * Self-refresh capability (L-ver only) * Fast paralleltest mode capability * TTL compatible inputs and outputs Unit : mW * Early Write or output enable controlled write * JEDEC Standard pinout 2K 605 550 * Available in Plastic SOJ and TSOP(II) packages * Single +5V10% power supply
* Active Power Dissipation Refresh Cycle 4K -5 -6 495 440
Speed
FUNCTIONAL BLOCK DIAGRAM
* Refresh Cycles Part NO. C4003C C4103C Refresh cycle 4K 2K Refresh period Normal 64ms 32ms
Refresh Timer Refresh Control Row Decoder Sense Amps & I/O RAS CAS0 - 3 W Control Clocks Vcc Vss
L-ver 128ms
VBB Generator
Data in Buffer
* Performance Range Speed -5 -6
Refresh Counter
tRAC
50ns 60ns
tCAC
13ns 15ns
tRC
90ns 110ns
tPC
35ns 40ns
Remark 5V/3.3V 5V/3.3V
Memory Array 4,194,304 x 4 Cells
DQ0 to DQ3
A0-A11 (A0 - A10) *1 A0 - A9 (A0 - A10) *1
Row Address Buffer Col. Address Buffer Column Decoder
Data out Buffer OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
KM44C4003C, KM44C4103C
CMOS DRAM
PIN CONFIGURATION (Top Views)
* KM44C40(1)03CK
* KM44C40(1)03CS
VCC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS DQ3 DQ2 CAS3 OE A9 CAS2 N.C A8 A7 A6 A5 A4 VSS
VCC DQ0 DQ1 W RAS *A11(N.C) CAS0 CAS1 A10 A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS DQ3 DQ2 CAS3 OE A9 CAS2 N.C A8 A7 A6 A5 A4 VSS
*A11 is N.C for KM44C4103C(5V, 2K Ref. product) K : 300mil 28 SOJ S : 300mil 28 TSOP II
Pin Name A0 - A11 A0 - A10 DQ0 - 3 VSS RAS CAS0~CAS3 W OE VCC N.C
Pin Function Address Inputs (4K Product) Address Inputs (2K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+5.0V) No Connection
KM44C4003C, KM44C4103C
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT VCC Inputs Tstg PD IOS Rating -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50
CMOS DRAM
Units V V C W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0*2 Typ 5.0 0 Max 5.5 0 VCC+1.0*1 0.8 Units V V V V
*1 : VCC+2.0V/20ns, Pulse width is measured at VCC *2 : -2.0/20ns, Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVIN+0.5V, all other input pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V
KM44C4003C, KM44C4103C
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed -5 -6 Dont care -5 -6 -5 -6 Dont care -5 -6 Dont care Dont care Max KM44C4003C 90 80 2 1 90 80 80 70 1 250 90 80 300 250 KM44C4103C 110 100 2 1 110 100 90 80 1 250 110 100 300 250
CMOS DRAM
Units mA mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA
ICC1
Dont care Normal L Dont care
ICC2
ICC3
ICC4
Dont care Normal L Dont care L L
ICC5
ICC6 ICC7 ICCS
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, DQ=Dont care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns ICCS : Self Refresh Current RAS=CAS=0.2V, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.
KM44C4003C, KM44C4103C
CAPACITANCE (TA=25C, VCC=5V, f=1MHz)
Parameter Input capacitance [A0 ~ A11] Input capacitance [RAS, CASx, W, OE] Output capacitance [DQ0 - DQ3] Symbol CIN1 CIN2 CDQ Min -
CMOS DRAM
Max 5 7 7 Units pF pF pF
AC CHARACTERISTICS (0CTA70C, See note 1,2)
Test condition : VCC=5.0V10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to Read command hold time referenced to Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Symbol Min -5 Max Min 110 155 50 13 25 0 0 3 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 13 13 10K 37 25 10K 13 50 0 0 3 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 10K 45 30 10K 15 50 60 15 30 -6 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 17 8,15 8 14 16 16 14 17 23 4,16 10 15 3,4,10 3,4,5,18 3,10 3,18 6 2 Units Notes
tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL
90 133
KM44C4003C, KM44C4103C
AC CHARACTERISTICS (Continued)
Parameter Data set-up time Data hold time Refresh period (2K, Normal) Refresh period (4K, Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast Page mode cycle time Fast Page read-modify-write cycle time CAS precharge time (Fast Page cycle) RAS pulse width (Fast Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Hold time CAS low to CAS high Symbol Min -5 Max Min 0 10 32 64 128 0 36 73 48 53 5 10 5 30 35 76 10 50 30 13 13 0 13 10 10 10 10 100 90 -50 5 13 15 0 15 10 10 10 10 100 110 -50 5 15 200K 40 85 10 60 35 15 0 40 85 55 60 5 10 5 35 32 64 128 -6 Max
CMOS DRAM
Units ns ns ms ms ms ns ns ns ns ns ns ns ns ns ns ns ns 200K ns ns ns ns ns ns ns ns ns ns us ns ns ns
Notes 9 9
tDS tDH tREF tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS tCLCH
0 10
7,16 7,14 7 7 7 16 15 16 3,15 19 19 20
21 22 6
11 11
25,26,27 25,26,27 25,26,27 13,24
KM44C4003C, KM44C4103C
TEST MODE CYCLE
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column address to RAS lead time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time Fast Page mode cycle time Fast Page read-modify-write cycle time RAS pulse width (Fast Page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -5 Max Min 115 160 55 18 30 55 18 18 55 30 41 78 53 58 40 81 55 200K 35 18 18 18 20 20 10K 10K 65 20 20 65 35 45 90 60 65 45 90 65 65 20 35 10K 10K -6 Max
CMOS DRAM
( Note 11 )
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 200K 40 20 ns ns ns ns ns 3 7 7 7 7 3,4,10,12 3,4,5,12 3,10,12 Notes
tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tCPWD tPC tPRWC tRASP tCPA tOEA tOED tOEH
95 138
KM44C4003C, KM44C4103C
NOTES
CMOS DRAM
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min), tAWDtAWD(min) and tCPWDtCPWD(min), then the cycle is a readmodify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. tRCH and tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the first CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the values of tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet. 13. In order to hold the address latched by the first CAS going low, the parameter tCLCH must be met. 14. The last CASx edge to go low. 15. The last CASx edge to go high. 16. The first CASx edge to go low. 17. The first CASx edge to go high. 18. Output parameter is refrenced to corresponding CASx input. 19. The last rising CASx edge to next cycles last rising CASx edge. 20. The last rising CASx edge to first falling CASx edge. 21. The first DQx controlled by the first CASx to go low. 22. The last DQx controlled by the last CASx to go high. 23. Each CASx must meet minimum pulse width. 24. The last falling CASx edge to the first rising CASx edge. 25. If tRASS100us, then RAS precharge time must use tRPS instead of tRP. 26. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/2048(2K) cycles of burst refresh must be executed within 64ms/32ms before and after self refresh, in order to meet refresh specification. 27. For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
KM44C4003C, KM44C4103C
READ CYCLE
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS0 VIH VIL -
tRCD tCAS
tRSH
tCRP
tCRP
CAS1 VIH VIL -
tCRP
CAS2 VIH VIL -
tCRP
CAS3 VIH VIL -
tCLCH
tRAD tASR
A VIH VIL -
tRAH
tASC
tRAL tCAH
COLUMN ADDRESS
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH tROH tAA tOEZ tOEA tCAC tOFF
OE
VIH VIL -
DQ0 ~ DQ3 VIH VIL -
tRAC OPEN
tCLZ
DATA-OUT
tOLZ
Dont care Undefined
KM44C4003C, KM44C4103C
WRITE CYCLE ( EARLY WRITE )
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS0 VIH VIL -
tCRP tRSH tCAS
tRCD
tCRP
CAS1 VIH VIL -
tCRP
CAS2 VIH VIL -
tCRP
CAS3 VIH VIL -
tCLCH tCSH tASC tRAL tCAH
COLUMN ADDRESS
tRAD tASR
A VIH VIL -
tRAH
ROW ADDRESS
tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ3 VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
KM44C4003C, KM44C4103C
WRITE CYCLE ( OE CONTROLLED WRITE )
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS0 VIH VIL -
tCRP tRSH tCAS
tRCD
tCRP
CAS1 VIH VIL -
tCRP
CAS2 VIH VIL -
tCRP
CAS3 VIH VIL -
tCLCH tRAD tASR tRAH tASC tRAL tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
OE
VIH VIL -
tOED tDS
tOEH tDH
DATA-IN
DQ0 ~ DQ3 VIH VIL -
Dont care Undefined
KM44C4003C, KM44C4103C
READ - MODIFY - WRTIE CYCLE
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS0 VIH VIL -
tCRP tRSH tCAS
tRCD
tCRP
CAS1 VIH VIL -
tCRP
CAS2 VIH VIL -
tCRP
CAS3 VIH VIL -
tCLCH tRAD tASR tRAH tASC tRAL tCAH
COLUMN ADDRESS
A
VIH VIL -
ROW ADDRESS
tAWD tCWD
W VIH VIL -
tRWL tCWL tWP
tRWD
OE VIH VIL -
tOEA tCLZ tCAC
DQ0 ~ DQ3 VOH VOL -
tAA tRAC
tOED tOEZ
VALID DATA-OUT
tDS
tDH
VALID DATA-IN
tOLZ
Dont care Undefined
KM44C4003C, KM44C4103C
FAST PAGE READ CYCLE
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tRHCP
tCRP
CAS0 VIH VIL VIH CAS1 VIL VIH CAS2 VIL VIH CAS3 VIL -
tPC tRCD tCAS tASC tCLCH tCP
o
tPC tCP tRSH tCAS
tCAS
o
tCAS
o
tRAD tCSH tASR tRAH tCAH
COLUMN ADDRESS
o
tASC
tCAH
o o
tASC
tCAH
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
tRCS
W VIH VIL -
tRCH tAA tOEA
tRCS tAA tCPA
tRCH
o
tRRH tRCS tAA tCPA tRCH
OE
VIH VIL -
o o
tCAC tRAC tCLZ tOEZ
VALID DATA-OUT
tCLZ
o
tOEZ
VALID DATA-OUT
tOEZ
VALID DATA-OUT
DQ0
VIH VIL VIH VIL VIH VIL VIH VIL -
tCLZ
VALID DATA-OUT
tOEZ
o
VALID DATA-OUT
DQ1
tCLZ
VALID DATA-OUT
tCLZ
o
VALID DATA-OUT
DQ2
tOLZ
tCLZ
o
VALID DATA-OUT
DQ3
Dont care Undefined
KM44C4003C, KM44C4103C
FAST PAGE WRITE CYCLE ( EARLY WRITE )
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tRHCP
tCRP
CAS0 VIH VIL VIH VIL VIH VIL VIH VIL -
tPC tRCD tCAS tCP
o
tPC tCP tRSH tCAS
tCAS
o
CAS1
tCAS
o
tCAS
CAS2
tCAS
tCAS
o
CAS3
tRAD tASC tASR tRAH
tCAS
o
tCSH tCAH
COLUMN ADDRESS
tASC
tCAH
o o
tASC
tCAH
A
VIH VIL -
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH tWP
tWCS tWP
tWCH
o
tWCS
tWCH tWP
OE
VIH VIL -
o o
tDS
DQ0 VIH VIL VIH VIL VIH VIL VIH VIL -
tDH
tDS
tDH
o
tDS
tDH
VALID DATA-IN
VALID DATA-IN
o o
VALID DATA-IN
tDS
DQ1
tDH
o
tDS
tDH
VALID DATA-IN
VALID DATA-IN
tDS
DQ2
tDH
tDS
tDH
o
VALID DATA-IN
VALID DATA-IN
o o
tDS
DQ3
tDH
VALID DATA-IN
o
Dont care Undefined
KM44C4003C, KM44C4103C
FAST PAGE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP tPRWC tRSH tCRP
tRCD
CAS0 VIH VIL VIH VIL VIH VIL VIH VIL -
tCP tCAS tCAS
CAS1
tCLCH
tCAS
CAS2
tCAS
tCAS
CAS3
tCAS tRAD tRAH tASC
COL. ADDR
tCLCH
tCSH tCAH tRAL tASC
COL. ADDR
tASR
A VIH VIL ROW ADDR
tCAH
tRCS
W VIH VIL -
tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tCWD tAWD tOEA tCAC tAA tOEZ tOED
tRWL tCWL tWP
OE
VIH VIL -
tDH tDS
DQ0 ~ DQ3 VIH VIL -
tRAC tCLZ
tCLZ
VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN
Dont care Undefined
KM44C4003C, KM44C4103C
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC
CMOS DRAM
tRAS
RAS VIH VIL -
tRP
tCRP
CASX VIH VIL -
tRPC
tCRP
tASR
A VIH VIL ROW ADDR
tRAH
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Dont care tRC tRP
RAS VIH VIL -
tRAS
tRP
tRPC tCP tRPC tCSR tWRP tWRH tCHR
CASX
VIH VIL -
W
VIH VIL -
DQ0 ~ DQ3 VIH VIL -
tOFF OPEN
Dont care Undefined
KM44C4003C, KM44C4103C
HIDDEN REFRESH CYCLE ( READ )
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRC tRP tRAS tRP
tCRP
CASX VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tWRH tRCS
W VIH VIL -
tAA
OE VIH VIL -
tOEA tCAC tRAC tCLZ tOEZ
DATA-OUT
tOFF
DQX
VIH VIL -
OPEN
Dont care Undefined
KM44C4003C, KM44C4103C
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC
RAS VIH VIL -
tRC tRP tRAS tRP
tRAS
tCRP
CASX VIH VIL -
tRCD tRAD
tRSH
tCHR
tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
tDS
DQX VIH VIL DATA-IN
tDH
Dont care Undefined
KM44C4003C, KM44C4103C
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Dont care
CMOS DRAM
tRP
RAS VIH VIL -
tRASS
tRPS tRPC tCHS
tRPC tCP
CASX
VIH VIL -
tCSR
DQ0 ~ DQ3 VOH VOL -
tOFF OPEN
TEST MODE IN CYCLE
NOTE : OE, A = Dont care
tRC tRP
RAS VIH VIL -
tRAS
tRP
tRPC tCP tRPC tCSR tWTS tWTH tCHR
CASX
VIH VIL -
W
VIH VIL -
DQ0 ~ DQ3 VIH VIL -
tOFF OPEN
Dont care Undefined
KM44C4003C, KM44C4103C
PACKAGE DIMENSION
28 SOJ 300mil
CMOS DRAM
Units : Inches (millimeters)
#28 0.330 (8.39) 0.340 (8.63) 0.300 (7.62) 0.260 (6.61) 0.280 (7.11)
0.006 (0.15) 0.012 (0.30)
#1 0.027 (0.69) MIN 0.741 (18.82) MAX 0.720 (18.30) 0.730 (18.54) 0.148 (3.76) MAX 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53)
0.0375 (0.95)
0.050 (1.27)
28 TSOP(II) 300mil
Units : Inches (millimeters)
0.355 (9.02) 0.371 (9.42)
0.300 (7.62)
0.004 (0.10) 0.010 (0.25)
0.741 (18.81) MAX 0.721 (18.31) 0.729 (18.51) 0.047 (1.20) MAX 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8
O
0.037 (0.95)
0.050 (1.27)
0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50)

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